Method of reading memory cell

ABSTRACT

A method for reading a memory cell ( 20 ) of a semiconductor memory ( 10 ) includes initiating a precharge or predischarge operation on a bit line ( 24 ) prior to arrival of a triggering edge of a clock signal ( 32 ) that initiates a read operation. A word line ( 22 ) is activated responsive to the triggering edge of the clock signal ( 32 ), and data is read from the memory cell ( 20 ).

BACKGROUND OF THE INVENTION

The present invention relates generally to semiconductor memories andmore particularly to a method of reading a memory cell of asemiconductor memory.

The access time of a semiconductor memory is typically determined bysumming clock-to-word line delay and word line-to-output delay. However,where precharging or predischarging is required for an access operation,the access time is determined by summing the word line-to-output delaytogether with the greater of either the clock-to-word line delay orclock-to-precharge/predischarge termination time. In such instances, theaccess time is often largely dependent on theclock-to-precharge/predischarge termination time, as theclock-to-precharge/predischarge termination time is usuallysubstantially greater than the clock-to-word line delay. Consequently,the access time of such semiconductor memories often cannot be improvedby optimizing the clock-to-word line delay since the access time isdetermined using the clock-to-precharge/predischarge termination time,and not the clock-to-word line delay.

Further, as technology scales, bit line resistance becomes increasinglymore dominant, lengthening the clock-to-precharge/predischargetermination time in, for example, ultra-deep sub-micron (UDSM)technologies at or below 90 nanometers (nm). This increases memoryaccess time, particularly of memory instances that have a large numberof memory cells coupled to each bit line.

Hence, there is a need for a precharging or predischarging scheme thatis operable to reduce memory access times, and thereby increasesemiconductor memory speeds.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description of a preferred embodiment of theinvention will be better understood when read in conjunction with theappended drawings. The present invention is illustrated by way ofexample and is not limited by the accompanying figures.

FIG. 1 is a schematic block diagram of a portion of a semiconductormemory in accordance with an exemplary embodiment of the presentinvention;

FIGS. 2A through 2C are schematic circuit diagrams illustrating aprecharge pulse generating circuit for the semiconductor memory of FIG.1; and

FIG. 3 is a timing diagram illustrating an operation to read a memorycell of the semiconductor memory of FIG. 1 using the precharge pulsegenerating circuit of FIGS. 2A through 2C.

DETAILED DESCRIPTION OF THE INVENTION

The detailed description set forth below in connection with the appendeddrawings is intended as a description of the presently preferredembodiment of the invention, and is not intended to represent the onlyform in which the present invention may be practiced. It is to beunderstood that the same or equivalent functions may be accomplished bydifferent embodiments that are intended to be encompassed within thespirit and scope of the invention.

The present invention is directed to a method for reading a memory cellof a semiconductor memory. The method includes initiating a precharge orpredischarge operation on a bit line prior to arrival of a triggeringedge of a clock signal that initiates a read operation. A word line isactivated responsive to the triggering edge of the clock signal, anddata is read from the memory cell.

The present invention is also directed to a method for reading a memorycell of a zero current leakage type read-only memory (ROM). The methodincludes initiating a precharge or predischarge operation on a bit lineprior to arrival of a triggering edge of a clock signal that initiates aread operation. A word line is activated responsive to the triggeringedge of the clock signal, and data is read from the memory cell.

The present invention is further directed to a method for reading amemory cell of a zero current leakage type ROM including initiating aprecharge or predischarge operation on a bit line and terminating theprecharge or predischarge operation prior to word line activation. Aword line is activated responsive to the triggering edge of the clocksignal, and data is read from the memory cell.

The present invention is further yet directed to a semiconductor memoryincluding a plurality of memory cells electrically connected in a matrixarrangement to a plurality of word lines and a plurality of bit lines. Aprecharge or predischarge pulse generating circuit is configured togenerate a precharge or predischarge pulse that initiates a precharge orpredischarge operation on at least one of the bit lines prior to arrivalof a triggering edge of a clock signal that initiates a read operation.Sensing circuitry is configured to sense data on the bit lines. Aplurality of reference memory cells may be electrically connected to areference bit line and respective ones of the word lines.

The precharging or predischarging scheme of the present invention hasseveral advantages. In particular, by initiating the precharge orpredischarge operation prior to the arrival of the triggering edge ofthe clock signal that initiates the read operation, a portion or all ofthe time required for the precharging or predischarging operation isshifted ahead of the clock arrival time. This reduces theclock-to-precharge/predischarge termination time, thereby enablingcomputation of memory access time independently of theclock-to-precharge/predischarge termination time. Advantageously, memoryaccess time may thus be reduced and further reduction in memory accesstime is possible by simply reducing the clock-to-word line delay.

Referring now to FIG. 1, a schematic block diagram of a portion of asemiconductor memory 10 in accordance with an exemplary embodiment ofthe present invention is shown.

The semiconductor memory 10 includes a first memory array 12, a secondmemory array 14, and a reference column 16 having a plurality ofreference memory cells 18. Each of the first and second memory arrays 12and 14 includes a plurality of memory cells 20 electrically connected ina matrix arrangement to a plurality of word lines (WLs) 22 and aplurality of bit lines (BLs) 24. The reference memory cells 18 areelectrically connected to respective ones of the WLs 22 and a referencebit line (RBL) 26. For clarity purposes, not all the reference memorycells 18, memory cells 20, WLs 22 and BLs 24 are shown in FIG. 1.Nonetheless, as will be understood by those of ordinary skill in theart, the first and second memory arrays 12 and 14 and the referencecolumn 16 may include any desired number of reference memory cells 18,memory cells 20, WLs 22 and BLs 24.

The first and second memory arrays 12 and 14 and the reference column 16share and are coupled to control circuitry 28 via row decoder (XDEC)circuitry 30. The control circuitry 28 receives a clock (CLK) signal 32and generates a word line clock (WLCLK) signal 34 that is used by theXDEC circuitry 30 along with other address signals to select aparticular WL 22 for activation. The control circuitry 28 and the XDECcircuitry 30 are well known to those of ordinary skill in the art.Therefore, detailed description thereof is not required for a completeunderstanding of the present invention.

The first memory array 12 is coupled to a first input/output (IO)section 36, and the second memory array 14 is coupled to a second IOsection 38. Each of the first and second IO sections 36 and 38 includessensing circuitry 40 configured to sense data on the BLs 24. The sensingcircuitry 40 may comprise any conventional sensing circuitry forsemiconductor memories. Accordingly, detailed description of the sensingcircuitry 40 is not required for a complete understanding of the presentinvention. An output (Q) 42 may be read from the first and second IOsections 36 and 38.

In the embodiment shown, precharging circuitry 44 is included in thefirst and second IO sections 36 and 38. The precharging circuitry 44 isconfigured to precharge the BLs 24 to a precharge voltage level. Forclarity purposes, only one (1) precharging circuit 44 is illustrated inFIG. 1. Nonetheless, as will be understood by those of ordinary skill inthe art, the first and second IO sections 36 and 38 may include anydesired number of precharging circuits 44, depending, for example, onthe number of BLs 24 in the first and second memory arrays 12 and 14.Further, although illustrated as part of the first and second IOsections 36 and 38 in FIG. 1, it should be understood that the presentinvention is not limited by the position of the precharging circuitry 44relative to the other elements of the semiconductor memory 10. Forinstance, the precharging circuitry 44 may be incorporated as part ofthe first and second memory arrays 12 and 14 in an alternativeembodiment.

The reference column 16 is coupled to a reference IO section 46. Thereference IO section 46 includes a precharge pulse generating circuit48. The precharge pulse generating circuit 48 is configured to receive achip enable (CHIP_ENABLE) signal 50 and a reset clock (RESET_CLK) signal52. The precharge pulse generating circuit 48 is further configured togenerate a precharge clock (PRCLKB) signal 54 and a precharge pulse(PRCHOFF) 56 for initiating and terminating precharging operations onthe BLs 24 and the RBL 26. Accordingly, as shown in FIG. 1, the PRCLKBsignal 54 and the PRCHOFF pulse 56 generated by the precharge pulsegenerating circuit 48 are transmitted to the precharging circuitry 44 inthe first and second IO sections 36 and 38 to enable or disable theprecharging circuitry.

The semiconductor memory 10 may be a zero current leakage type read-onlymemory (ROM) or any other suitable memory type known to those ofordinary skill in the art. Although illustrated as having a referencecolumn 16, it should be understood by those of ordinary skill in the artthat the present invention is not limited to the described circuitconfiguration. For example, the semiconductor memory 10 may include areference word line coupled to a reference bit line in one alternativeembodiment and may not include any reference lines in another.

In the present embodiment, circuitry in the reference column 16 and thereference IO section 46 mimics actual access operations within thesemiconductor memory 10. Correspondingly, the precharge pulse generatingcircuit 48 mimics precharging operations on the actual BLs 24.Advantageously, this allows the precharge pulse generating circuit 48 togenerate an appropriate PRCHOFF pulse 56 for controlling the prechargingoperations on the actual BLs 24, thereby overcoming the difficulty indetermining when precharging of the multiple BLs 24 is sufficientlycomplete for precharging to be stopped. Nonetheless, althoughillustrated as part of the reference IO section 46 in FIG. 1, it shouldbe understood that the present invention is not limited by the positionof the precharge pulse generating circuit 48 relative to the otherelements of the semiconductor memory 10. The precharge pulse generatingcircuit 48 may be provided in other sections of the semiconductor memory10 such as, for example, the control circuitry section 28 in otherembodiments.

The RESET_CLK signal 52 may be configured to ensure that all signalswithin the semiconductor memory 10 revert to their steady state ordefault values in anticipation of a next memory access cycle. In oneembodiment, the RESET_CLK signal 52 may be generated by a self-timingcircuit (not shown) in the control circuitry section 28 or derived froma falling edge of an external clock signal.

The precharge pulse generating circuit 48 will now be described ingreater detail below with reference to the schematic circuit diagrams ofFIGS. 2A through 2C illustrating an exemplary precharge pulse generatingcircuit 48 for the semiconductor memory 10 of FIG. 1.

Referring now to FIG. 2A, a first portion 100 of the precharge pulsegenerating circuit 48 is shown. The first portion 100 of the prechargepulse generating circuit 48 includes a plurality of inverters 102, 104,106 and 108 coupled in series, a first feedback inverter 110, and afirst reset transistor 112. A first of the inverters 102 is configuredto receive the CHIP_ENABLE signal 50 and a fourth of the inverters 108is configured to output a latch signal (PS_LATCH) 114. The PS_LATCHsignal 114 is fed back through the first feedback inverter 110 as aninput to the fourth inverter 108 to hold the PS_LATCH signal 114. Theoutput of the first feedback inverter 110 is also coupled to the firstreset transistor 112. A gate of the first reset transistor 112 isconfigured to receive the RESET_CLK signal 52.

Although four (4) series-coupled inverters 102, 104, 106 and 108 areshown in FIG. 2A, it will be understood by those of skill in the artthat the present invention is not limited to four gate delays. Theduration of the delay may be shortened or lengthened in alternativeembodiments by employing fewer or greater numbers of series-coupledinverters depending, for example, on the input pin capacitance and/orinput pin hold time.

In the embodiment shown, the first reset transistor 112 is a p-typetransistor having a drain coupled to an output of the first feedbackinverter 110 and a source coupled to a supply voltage VDD. It shouldhowever be understood by those of ordinary skill in the art that thepresent invention is not limited by the type of transistor employed.

Referring now to FIG. 2B, a second portion 130 of the precharge pulsegenerating circuit 48 is shown. The second portion 130 of the prechargepulse generating circuit 48 includes a first transistor 132 coupledbetween a second transistor 134 and a second reset transistor 136. Agate of the first transistor 132 is configured to receive the PS_LATCHsignal 114 from the first portion 100 of the precharge pulse generatingcircuit 48. An input of a fifth inverter 138 is coupled to a node 140between the first transistor 132 and the second reset transistor 136.The fifth inverter 138 is configured to output a common precharge signalPS_COM 142. The PS_COM signal 142 is fed back through a second feedbackinverter 144 as an input to the fifth inverter 138 to hold the PS_COMsignal 142. The PS_COM signal 142 is also fed back through a thirdfeedback inverter 146 to a gate of the second transistor 134. A gate ofthe second reset transistor 136 is configured to receive the RESET_CLKsignal 52.

In the embodiment shown, the first and second transistors 132 and 134are n-type transistors and the second reset transistor 136 is a p-typetransistor. A source of the first transistor 132 is coupled to a drainof the second transistor 134, and a drain of the first transistor 132 iscoupled to a drain of the second reset transistor 136 at node 140. Asource of the second transistor 134 is coupled to ground, and a sourceof the second reset transistor 136 is coupled to the supply voltage VDD.Nonetheless, it should be understood by those of ordinary skill in theart that the present invention is not limited by the types oftransistors employed.

Referring now to FIG. 2C, a third portion 160 of the precharge pulsegenerating circuit 48 is shown. The third portion 160 of the prechargepulse generating circuit 48 includes a sixth inverter 162 and a NANDgate 164. The PS_COM 142 signal from the second portion 130 of theprecharge pulse generating circuit 48 is received as an input to thesixth inverter 162 and as a first input to the NAND gate 164. The sixthinverter 162 is configured to output the PRCLKB signal 54, and the NANDgate 164 is configured to output the PRCHOFF pulse 56.

The PRCLKB signal 54 and the PRCHOFF pulse 56 are received as inputs toan RBL precharge circuit 166. The RBL precharge circuit 166 comprises athird transistor 168 and a fourth transistor 170 coupled at a node 172to the RBL 26. A gate of the third transistor 168 is configured toreceive the PRCLKB signal 54, and a gate of the fourth transistor 170 isconfigured to receive the PRCHOFF pulse 56.

The PRCLKB signal 54 is also received as an input to a seventh inverter174. An output of the seventh inverter 174 is received at a gate of afifth transistor 176. A sixth transistor 178 having a gate coupled tothe RBL 26 is coupled to the fifth transistor 176 at a node 180.

A programmable delay circuit 182 is coupled between the fifth and sixthtransistors 176 and 178 at node 180. An output of the programmable delaycircuit 182 is received as a second input to the NAND gate 164. A gateof a seventh transistor 184 is coupled to the programmable delay circuit182.

In the present embodiment, the third, sixth and seventh transistors 168,178 and 184 are n-type transistors and the fourth and fifth transistors170 and 176 are p-type transistors. A source of the third transistor 168is coupled to ground, and a drain of the third transistor 168 is coupledto a drain of the fourth transistor 170 at node 172. Sources of thefourth and fifth transistors 170 and 176 are coupled to the supplyvoltage VDD. A drain of the fifth transistor 176 is coupled to a drainof the sixth transistor 178 at node 180. A source of the sixthtransistor 178 is coupled to ground. A drain of the seventh transistor184 is coupled to an input of the programmable delay circuit 182, and asource of the seventh transistor 184 is coupled to ground. It shouldhowever be understood by those of ordinary skill in the art that thepresent invention is not limited by the types of transistors employed.

In the embodiment shown, the programmable delay circuit 182 includes aneighth inverter 186 and a ninth inverter 188 connected in series. Anoutput of the eighth inverter 186 is received at the gate of the seventhtransistor 184. Although illustrated as having two (2) inverters in FIG.2C, it will be understood by those of skill in the art that the presentinvention is not limited to a programmable delay circuit 182 having onlytwo gate delays. The duration of the delay may be programmed bylengthening or shortening the delay chain in the programmable delaycircuit 182.

The transistors in FIGS. 2A through 2C may also include a bulk terminal.Unless noted otherwise, the bulk terminals of the n-type transistors areconnected to ground and that of the p-type transistors are connected tothe supply voltage VDD.

Having described the various components of the precharge pulsegenerating circuit 48, an operation to read one of the memory cells 20of the semiconductor memory 10 of FIG. 1 storing a LOW logic value usingthe precharge pulse generating circuit 48 of FIGS. 2A through 2C willnow be described below with reference to the timing diagram 200 of FIG.3.

Referring now to FIG. 3, the timing diagram 200 includes a signalrepresentative of the CHIP_ENABLE signal 50 (FIGS. 1 and 2A), a signalrepresentative of the PS_LATCH signal 114 (FIGS. 2A and 2B), a signalrepresentative of the PS_COM signal 142 (FIGS. 2B and 2C), a signalrepresentative of an active low PRCLKB signal 54 (FIGS. 1 and 2C), asignal representative of an active low PRCHOFF pulse 56 (FIGS. 1 and2C), a signal 202 representative of the voltage level on the RBL 26(FIGS. 1 and 2C), a signal 204 representative of an active lowprecharging pulse PRCHOFF_FAR received by precharging circuitry 44coupled to a BL 24 along a critical path, that is, the BL 24 furthestfrom the precharge pulse generating circuit 48 (FIG. 1), a signal 206representative of the voltage level on the BL 24 along the critical path(FIG. 1), a signal representative of the CLK signal 32 (FIG. 1), asignal representative of the assertion of a WL 22, a signal 208representative of the assertion of a WL 22 along the critical path, thatis, the WL 22 furthest from the control circuitry 28 (FIG. 1), a signalrepresentative of the output Q 42 read out from the memory cell 20 (FIG.1), and a signal representative of the RESET_CLK signal 52 (FIGS. 1, 2Aand 2B).

At time t₀ (time 210), the CHIP_ENABLE signal 50 is asserted or pulledhigh. This causes the PS_LATCH signal 114 to be pulled high at time t₁(time 212), switching on the first transistor 132. Consequently, node140 is pulled low and the PS_COM signal 142 is pulled high at time t₂(time 214).

A low signal is received at the gate of the second transistor 134. Thisswitches the second transistor 134 off, locking the value of the PS_COMsignal 142 on the rising edge of the PS_LATCH signal 114. Consequently,the PS_COM signal 142 is not impacted if the PS_LATCH signal 114subsequently goes low, for example, when the CHIP_ENABLE signal 50 ispulled down.

When the PS_COM signal 142 is pulled high at time t₂ (time 214), boththe PRCLKB signal 54 and the PRCHOFF pulse 56 are pulled low, andprecharging of the RBL 26 is initiated.

The PRCLKB signal 54 and the PRCHOFF pulse 56 are transmitted to theprecharging circuitry 44. Consequently, at time t₃ (time 216), thePRCHOFF_FAR pulse is pulled low, initiating a precharge operation on theBL 24 in the critical path prior to arrival of a triggering edge of theCLK signal 32 that initiates the read operation.

The seventh inverter 174 receives the low PRCLKB signal 54 and outputs ahigh signal to the gate of the fifth transistor 176. This switches thefifth transistor 176 off.

Consequent to the precharge operation on the RBL 26, the sixthtransistor 178 is switched on after a period of time, and node 180 ispulled low.

After a period of delay imparted by the programmable delay circuit 182,the second input to the NAND gate 164 is pulled low, and the PRCHOFFpulse 56 output from the NAND gate 164 is pulled high at time t₄ (time218), terminating the precharging operation on the RBL 26.

The change in the PRCHOFF pulse 56 is transmitted to the prechargingcircuitry 44. Consequently, at time t₅ (time 220), the PRCHOFF_FAR pulseis pulled high, terminating the precharge operation on the BL 24 in thecritical path.

At time t₆ (time 222), the CLK signal 32 is asserted or pulled high. AWL 22 is activated at time t₇ (time 224) responsive to the triggeringedge of the CLK signal 32 and, consequently, discharge of the BL 24 isinitiated. The triggering edge of the CLK signal 32 is propagated toother WLs 22 and at time t₈ (time 226), the WL 22 in the critical pathis activated. Data is read from the memory cell 20 at time t₉ (time228).

At time t₁₀ (time 230), the RESET_CLK 52 is asserted or pulled low. Thisresets the PRCLKB signal 54, the PS_LATCH signal 114 and the PS_COMsignal 142 to their steady state or default values in anticipation ofthe next read cycle.

By initiating the precharge operation before the arrival of thetriggering edge of the CLK signal 32 that initiates the read operation,a portion or all of the time required for the precharging operation isshifted ahead of the clock arrival time t₆ (time 222) to the setup timeof the CHIP_ENABLE signal 50. In one embodiment, the precharge operationmay be initiated a worst case setup time before the arrival of thetriggering edge of the clock signal. For example, if the longest setuptime of all the pins of a semiconductor memory is between about 400picoseconds (ps) and about 800 ps, then the precharge operation may beinitiated between about 400 ps and about 800 ps before the arrival ofthe triggering edge of the clock signal. Advantageously, this reducesthe clock-to-precharge termination time, thereby enabling computation ofthe memory access time independently of the clock-to-prechargetermination time. Memory access time may thus be reduced and furtherreduction in memory access times is possible by simply reducing theclock-to-word line delay, for example, by reducing a gate count along apath from a clock input to the word line to less than or equal to aboutsix (6) gates.

In the present embodiment, the precharge operation on the BLs 24 and RBL26 is terminated before any of the WLs 22 are activated. Advantageously,this prevents an overlap of an active precharge signal with an active WLsignal, thereby preventing short circuit power dissipation.

In the embodiment shown, the precharge operation is initiated byasserting the CHIP_ENABLE signal 50. Accordingly, the prechargeoperation takes place during chip enable setup time. However, as will beunderstood by those of ordinary skill in the art, the present inventionis not limited to precharge initiation via the CHIP_ENABLE signal 50.The precharge operation may be initiated using other reference signalsor pins available to the semiconductor memory 10 or via a separatelyprovided precharge initiation signal or pin, in alternative embodiments.In one embodiment, the precharge operation may be initiated by assertingan asynchronous signal or pin. As such, the precharge operation may beperformed during a setup time of the semiconductor memory 10.

In one embodiment, the precharge pulse generating circuit 48 may beconfigured to generate a PRCHOFF pulse 56 that terminates the prechargeoperation when the BLs 24 and the RBL 26 are precharged to about 95percent (%) of the supply voltage VDD.

In the present embodiment, the read operation occurs in a clock highperiod and, consequently, the precharge operation is initiated during aclock low period. However, as will be understood by those of ordinaryskill in the art, this may be reversed in alternative embodiments, thatis, the read operation may occur in the clock low period and theprecharge operation may consequently be initiated during the clock highperiod.

Although a semiconductor memory 10 employing bit line precharging isdescribed in FIGS. 1 through 3, it should be understood by those ofordinary skill in the art that the present invention is not limited tomemories that employ bit line precharging. The present invention may beemployed in semiconductor memories that require predischarging before aread access operation in alternative embodiments. As such memories arewell known in the art, detailed description thereof is not required fora complete understanding of the present invention.

The description of the preferred embodiment of the present invention hasbeen presented for purposes of illustration and description, but is notintended to be exhaustive or to limit the invention to the formdisclosed. It will be appreciated by those skilled in the art thatchanges could be made to the embodiment described above withoutdeparting from the broad inventive concept thereof. It is understood,therefore, that this invention is not limited to the particularembodiment disclosed, but covers modifications within the spirit andscope of the present invention as defined by the appended claims.

1. A method for reading a memory cell of a semiconductor memory, comprising: initiating a precharge or predischarge operation on a bit line prior to arrival of a triggering edge of a clock signal that initiates a read operation; activating a word line responsive to the triggering edge of the clock signal; and reading data from the memory cell.
 2. The method for reading a memory cell of a semiconductor memory of claim 1, further comprising terminating the precharge or predischarge operation before activating the word line.
 3. The method for reading a memory cell of a semiconductor memory of claim 1, wherein the precharge or predischarge operation is initiated a worst case setup time before the arrival of the triggering edge of the clock signal.
 4. The method for reading a memory cell of a semiconductor memory of claim 3, wherein the precharge or predischarge operation is initiated between about 400 picoseconds (ps) and about 800 ps before the arrival of the triggering edge of the clock signal.
 5. The method for reading a memory cell of a semiconductor memory of claim 1, wherein the precharge or predischarge operation is performed during a setup time of the semiconductor memory.
 6. The method for reading a memory cell of a semiconductor memory of claim 1, wherein the precharge or predischarge operation is initiated by asserting a chip enable signal.
 7. The method for reading a memory cell of a semiconductor memory of claim 1, wherein the precharge or predischarge operation is initiated by asserting an asynchronous signal or pin.
 8. The method for reading a memory cell of a semiconductor memory of claim 1, wherein the semiconductor memory is a zero current leakage type read-only memory (ROM).
 9. A method for reading a memory cell of a zero current leakage type read-only memory (ROM), comprising: initiating a precharge or predischarge operation on a bit line prior to arrival of a triggering edge of a clock signal that initiates a read operation; activating a word line responsive to the triggering edge of the clock signal; and reading data from the memory cell.
 10. The method for reading a memory cell of a zero current leakage type ROM of claim 9, further comprising terminating the precharge or predischarge operation before activating the word line.
 11. The method for reading a memory cell of a zero current leakage type ROM of claim 9, wherein the precharge or predischarge operation is initiated a worst case setup time before the arrival of the triggering edge of the clock signal.
 12. The method for reading a memory cell of a zero current leakage type ROM of claim 11, wherein the precharge or predischarge operation is initiated between about 400 ps and about 800 ps before the arrival of the triggering edge of the clock signal.
 13. The method for reading a memory cell of a zero current leakage type ROM of claim 9, wherein the precharge or predischarge operation is performed during a setup time of the ROM.
 14. The method for reading a memory cell of a zero current leakage type ROM of claim 9, wherein the precharge or predischarge operation is initiated by asserting a chip enable signal.
 15. The method for reading a memory cell of a zero current leakage type ROM of claim 9, wherein the precharge or predischarge operation is initiated by asserting an asynchronous signal or pin.
 16. The method for reading a memory cell of a zero current leakage type ROM of claim 9, wherein a gate count along a path from a clock input to the word line is less than or equal to about six (6) gates.
 17. A method for reading a memory cell of a zero current leakage type read-only memory (ROM), comprising: initiating a precharge or predischarge operation on a bit line prior to arrival of a triggering edge of a clock signal that initiates a read operation; terminating the precharge or predischarge operation prior to word line activation; activating a word line responsive to the triggering edge of the clock signal; and reading data from the memory cell.
 18. The method for reading a memory cell of a zero current leakage type ROM of claim 17, wherein the precharge or predischarge operation is initiated a worst case setup time before the arrival of the triggering edge of the clock signal.
 19. The method for reading a memory cell of a zero current leakage type ROM of claim 17, wherein the precharge or predischarge operation is performed during a setup time of the ROM.
 20. The method for reading a memory cell of a zero current leakage type ROM of claim 17, wherein a gate count along a path from a clock input to the word line is less than or equal to about six (6) gates. 